1. Field of the Invention
The invention relates to a communication system of a type suitable for the transmission of digital information through a single channel information bus between two or more out of a number of, asynchronously operating, apparatus coupled to the information bus, each apparatus including at least a digital data processing portion having a clock generator for the generation of a periodic clock-signal, and the data processing portion being coupled by means of a digital control unit to the information bus in such manner that the transmission switches in the control units form an AND-gate circuit with the information bus. The invention also relates to a control unit for coupling an apparatus to the information bus.
2. Description of the Prior Art
Communication systems of the above type are usually used in situations where a plurality of apparatus share a transfer medium for intercommunication. This may be the communication between one or more intelligent terminals and a central computer in a laboratory, but the communication may also be for the control of domestic appliances, for example by means of a so-called "home-computer", audio and/or video equipment possibly being coupled to the information bus, both for the control of these appliances and for applying text data to a television receiver, these text data having been obtained by means of a teletext demodulator, or a viewdata terminal, etc.
Within computer systems the information bus may be a multi-channel bus through which digital information is transmitted in parallel.
When the average information density is sufficiently low, a single-channel bus will usually be sufficient, the information being transmitted serially. Low density applications are typically found in various interrelated consumer products such as home entertainment systems, home security systems and lower capability personal computer systems.
A communication system of the above type is known from the report on the "Second Symposium on Micro Architecture "Euromicro", 1976; pages 299-304, R. Sommer: "Cobus, a firmware controlled data transmission system".
This publication discloses a communication system in which the single-channel bus is in the form of a coaxial cable which, in combination with transmission switches connected thereto, forms an AND-gate circuit which is suitable for the transmission of information at a speed of approximately 200 kBaud, which means, minimum waiting periods, priority arbitration, addresses included, a net transmission capacity of approximately 10,000 information words, each consisting of 8 to 10 bits, per second.
As the bus circuit forms an AND-gate circuit, the bus will only be in the "ON" condition when all transmit switches keep the output in the "ON" position, which, in the case transistors are used as transmission switches, generally implies that the transmission switches do not carry current.
When a pulse is required, the transmission switch is rendered conductive by applying a current to its base, its output then going to the "OFF" state.
As soon as at least one transmission switch supplies an "OFF" pulse, the bus line is in the "OFF" state, irrespective of the positions of other transmission switches.
So-called "open collector" transmission switches are used which form a wired-AND function in combination with the coaxial cable.
The choice between "ON" or "OFF" is optional. In this article an AND-gate circuit is used in which the bus is in its "ON" state when all the coupled inputs are "ON". This definition will also be used in the further course of this description. It is well known that this definition is equivalent to an OR-gate circuit for "OFF" signals, the wired-OR function.
FIG. 2 of the cited SOMMER publication shows a simplified block-diagram of a microprocessor-controlled "Cobus interface", which, in the art, is usually indicated by the term "control-unit".
The Cobus-interface shown comprises inter alia a receiving circuit and an "interference detector". These circuits check whether another control unit simultaneously requests the bus line, by checking the transmitter's own address. A priority rule ensures that the apparatus having the lower address is given priority.
In addition, the control units include a "carrier detector", that is to say a circuit for reconstructing the bit clock and a synchronizing circuit. In the starting phases the bit rate is halved to reduce the effect of the synchronization problems due to inter alia the signal propagation time over the bus cable.
A carrier detector is usually formed by means of a so-called flywheel oscillator or a phase locked loop oscillator (PLLO).
This requires the use of a very stable clock generator, which can only be realized by the use of a crystal-controlled generator.
With a view to synchronization each word has a starting bit. Micro-synchronization as well as macro-synchronization occurs on the starting bit and on any other set bit, (R. Sommer, Cobus, a firmware controlled data transmission system, page 300, right-hand column, paragraph 5.2).
As a crystal-controlled clock generator is required at the transmitting end and a flywheel oscillator or a PLLO at the receiver end, the circuits are relatively expensive. They are suitable for the above-mentioned use in a laboratory but they are unacceptably expensive for use in simple systems. In the described system it is furthermore impossible to couple apparatus which operate with greatly different nominal speeds to one bus. Finally, the close time tolerances require well-defined and therefore steep pulse edges, so that a coaxial cable must be used as the bus line to render it possible to keep stray radiation to the environment at an acceptably low level.
A an inexpensive twisted two-wire system cannot be used in view of the requirements with respect to interference imposed by postal and similar authorities.